1. Field of the Invention
The present invention relates to Synchronous Dynamic Random Access Memories (SDRAMs), and particularly to Delay Lock Loop (DLL) circuitry employed within SDRAMs for obtaining double data rate (DDR) memory access.
2. State of the Art
In conventional synchronous DRAMs, the timing of when output data is made available or is clocked through the output buffer of the memory device is dependent on when valid data is available from the memory cell array. Specifically, in these conventional systems, data output timing is determined by the access time (tAC) and the output hold time (tOH) of the SDRAM. In order to ensure valid data, the output data is synchronized to be clocked from the output buffer during the time interval between tAC and tOH. This is achieved by designing the memory device with a predetermined delayed clock signal for clocking data through the memory device output buffers.
In an alternative SDRAM design, data output is synchronized to the subsequent rising and/or falling edge of the system clock. An example of this type of SDRAM design is a double data rate (DDR) SDRAM. The DDR SDRAM includes delay lock loop (DLL) circuitry for controlling the internal clock of the memory device so as to synchronized data output with the rising/falling edges of the external system clock. The DLL circuitry inserts an optimum delay time between the clock input buffer and the data output buffer making the data switch simultaneously with the external clock.
FIG. 1A shows a system block diagram of a SDRAM 10 design including DLL circuitry 11 which in response to external clock signal 11A provides an optimum delayed clock signal 11B to the output buffer 12 such that the data 12A from the DRAM core 13 is output from the buffer 12 on the rising and falling edge of the external clock 11A to provide Output Data signal 12B.
FIG. 1B shows a basic prior art digital DLL circuit design 14 including an input receiver buffer 15 for receiving an external clock signal 15A and providing an internal clock signal 15B to a Delay Unit circuit 16. The Delay Unit circuit 16 is adjustably controlled with digital data stored within a shift register 17. Delay Unit circuit 16 delays the internal clock signal 15B by the amount programmed into the shift register. Clock signal 16A is used to clock output buffer 18 such that data 18A from the DRAM core is clocked through buffer 18 on the subsequent rising and falling edges of the external clock signal 15A. The DLL circuit further includes a feedback loop having a Phase Detector 19 which detects the phase difference between a feedback clock signal 16A' and the internal clock signal 15B and generates the signals for controlling the shift register to shift left or right thereby increasing or decreasing the delay, respectively. Dummy output buffer 20 and Dummy receiver buffer 21 provide a path for feedback Clk signal 16A that is equivalent to the path that the external clock signal 15A passes through to the output of the system. The delay value stored in register 17 is used to control delay unit circuit 16 causing it to provide a delay such that data 18A is clocked through buffer 18 to the output of the memory device on each of the next rising or falling edge of the external clock signal.
In order to obtain the desired delay value in register 17 the delay lock loop must be set in a lock state in which there is no phase difference between the clock signal 15B and the feedback clock signal 16A', i.e. signals 15B and 16A' have synchronized rising and falling clock edge timing. When signals 15B and 16A' have synchronized timing then signal 15A and signal 9 also have synchronized timing since the timing of signal 15A and signal 9 correspond to the timing of signal 15B and signal 16A', respectively, minus the delay time contributed from equivalent delay receivers 15 and 21. In addition, since the timing of signal 9 is: EQU timing.sub.Data Out =timing.sub.15A +delay.sub.output buffer 18 EQU timing.sub.Data Out =timing.sub.15A +delay.sub.dummy output buffer 20
timing.sub.Data Out =timing.sub.9,
an since dummy buffer 20 provides an equivalent delay as output buffer 18, then the timing of signal 9 is synchronized with the timing of the Data Out Signal. Consequently, since signal 9 is synchronized with both of signals 15A and the Data Out Signal, then the External Clk Signal 15A is synchronized with the Data Out Signal when the DLL circuit is in a lock state thereby providing the desired function of synchronizing rising and falling clock edges of the external clock and the output data of the memory system.
The problem with current DLL circuit designs is that, upon start-up, they require a period of time for the feedback loop to obtain the lock state when there is no phase difference between the feedback signal 16A' and the internal clock signal 15B and the timing of the External Clock 15A is synchronized with the Data Out signal as described above. In this state, an optimum delay value is stored in the shift register 17. Obtaining a lock state can take as many as 100-200 clock cycles. In addition, these clock cycles significantly increase stand-by current consumption.
What would be desirable is to reduce the time it takes for the DLL circuit to obtain a lock state and to minimize stand-by current due to the DLL circuit in DRR SDRAM memory applications.